View MC-4516CA727XFA-A75A_6843345.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local elpida memory, inc. for availability and additional information. elpida memory, inc. 2001 c mos integrated circuit mc-4516ca727xfa 16m-word by 72-bit synchronous dynamic ram module unbuffered type data sheet document no. e0231n10 (ver. 1.0) date published november 2001 (k) japan elpida memory, inc. is a joint venture dram company of nec corporation and hitachi, ltd. description the mc-4516ca727 xfa is 16,777,216 words by 72 bits synchronous dynamic ram module on which 9 pieces of 128m sdram: pd45128841 are assembled. this module provides high density and large quantities of memory in a small space without utilizing the surface- mounting technology on the printed circuit board. decoupling capacitors are mounted on power supply line for noise reduction. features ? 16,777,216 words by 72 bits organization (ecc type) ? clock frequency and access time from clk part number /cas latency clock frequency access time from clk (max.) (max.) MC-4516CA727XFA-A75A cl = 3 133 mhz 5.4 ns cl = 2 133 mhz 5.4 ns mc-4516ca727xfa-a75 cl = 3 133 mhz 5.4 ns cl = 2 100 mhz 6.0 ns ? fully synchronous dynamic ram, with all signals referenced to a positive clock edge ? pulsed interface ? possible to assert random column address in every cycle ? quad internal banks controlled by ba0 and ba1 (bank select) ? programmable burst-length (1, 2, 4, 8 and full page) ? programmable wrap sequence (sequential / interleave) ? programmable /cas latency (2, 3) ? automatic precharge and controlled precharge ? cbr (auto) refresh and self refresh ? all dqs have 10 ? 10 % of series resistor ? single 3.3 v 0.3 v power supply ? lvttl compatible ? 4,096 refresh cycles/64 ms ? burst termination by burst stop command and precharge command ? 168-pin dual in-line memory module (pin pitch = 1.27 mm) ? unbuffered type ? serial pd
data sheet e0231n10 2 mc-4516ca727xfa ordering information part number clock package mounted devices (max.) MC-4516CA727XFA-A75A 133 mhz 168-pin dual in-line memory module 9 pieces of pd45128841g5 (rev. x) (socket type) (10.16 mm (400) tsop (ii)) mc-4516ca727xfa-a75 edge connector : gold plated 34.93 mm height
data sheet e0231n10 3 mc-4516ca727xfa pin configuration 168-pin dual in-line memory module socket type (edge connector: gold plated) 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 v ss dq32 dq33 dq34 dq35 vcc dq36 dq37 dq38 dq39 dq40 v ss dq41 dq42 dq43 dq44 dq45 vcc cb5 v ss nc nc vcc /cas dqmb4 dqmb5 nc /ras v ss a1 a3 a5 a7 a9 ba0 (a13) a11 vcc clk1 nc v ss cke0 nc dqmb6 dqmb7 nc vcc nc nc cb6 cb7 v ss dq48 dq49 dq50 dq51 vcc dq52 nc nc nc v ss dq53 dq54 dq55 v ss dq56 dq57 dq58 dq59 vcc dq60 dq61 dq62 dq63 v ss clk3 nc sa0 sa1 sa2 vcc dq46 dq47 cb4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 v ss dq0 dq1 dq2 dq3 vcc dq4 dq5 dq6 dq7 dq8 v ss dq9 dq10 dq11 dq12 dq13 vcc dq14 dq15 cb0 cb1 v ss nc nc vcc /we dqmb0 dqmb1 /cs0 nc v ss a0 a2 a4 a6 a8 a10 ba1 (a12) vcc vcc clk0 v ss nc /cs2 dqmb2 dqmb3 nc vcc nc nc cb2 cb3 v ss dq16 dq17 dq18 dq19 vcc dq20 nc nc nc v ss dq21 dq22 dq23 v ss dq24 dq25 dq26 dq27 vcc dq28 dq29 dq30 dq31 v ss clk2 nc nc sda scl vcc a0 - a11 : address inputs [row: a0 - a11, column: a0 C a9] ba0 (a13), ba1 (a12) : sdram bank select dq0 - dq63, cb0 - cb7 : data inputs/outputs clk0 - clk3 : clock input cke0 : clock enable input /cs0, /cs2 : chip select input /ras : row address strobe /cas : column address strobe /we : write enable dqmb0 - dqmb7 : dq mask enable sa0 - sa2 : address input for eeprom sda : serial data i/o for pd scl : clock input for pd v cc : power supply v ss : ground nc : no connection /xxx indicates active low si gnal.
data sheet e0231n10 4 mc-4516ca727xfa block diagram dqmb0 /cs0 /we dqmb2 /cs2 dqm d0 /cs /we dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 d1 dqm /cs /we dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 d2 dqm /cs /we dq 32 dq 33 dq 34 dq 35 dq 36 dq 37 dq 38 dq 39 dq 4 dq 7 dq 0 dq 2 dq 6 dq 5 dq 3 dq 1 d5 dqm /cs /we dq 40 dq 41 dq 42 dq 43 dq 44 dq 45 dq 46 dq 47 dq 4 dq 7 dq 6 dq 5 dq 3 dq 2 dq 1 dq 0 d6 dqm /cs /we dq 5 dq 7 dq 6 dq 4 dq 3 dq 2 dq 1 dq 0 d7 dqm /cs /we dq 56 dq 57 dq 58 dq 59 dq 60 dq 61 dq 62 dq 63 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 dq 7 d8 dqm /cs /we dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 d4 dqm /cs /we dq 48 dq 49 dq 50 dq 51 dq 52 dq 53 dq 54 dq 55 dq 7 dq 6 dq 5 dq 3 dq 2 dq 1 dq 0 dq 4 dqm d3 /cs /we dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 dq 7 cb 0 cb 1 cb 2 cb 3 cb 4 cb 5 cb 6 cb 7 dq 16 dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dqmb1 dqmb4 dqmb5 dqmb7 dqmb6 dqmb3 a0 - a11 a0 - a11 : d0 - d8 ba0 a13 : d0 - d8 ba1 a12 : d0 - d8 /ras /ras : d0 - d8 /cas /cas : d0 - d8 cke0 cke : d0 - d8 v cc d0 - d8 d0 - d8 ss v c clk1, clk3 10 pf clk2 clk : d3, d4, d7, d8 3.3 pf clk0 clk : d0, d1, d2, d5, d6 serial pd scl sda a0 a1 a2 sa0 sa1 sa2 remarks 1. the value of all resistors is 10 ? . 2. d0 - d8: pd45128841 (4m words 8 bits 4 banks)
data sheet e0231n10 5 mc-4516ca727xfa electrical specifications ? all voltages are referenced to v ss (gnd). ? after power up, wait more than 100 s and then, execute power on sequence and cbr (auto) refresh before proper device operation is achieved. absolute maximum ratings parameter s y mbol condition ratin g unit volta g e on p ower su pp l y p in relative to gnd v cc C0.5 to +4.6 v voltage on input pin relative to gnd v t C0.5 to +4.6 v short circuit output current i o 50 ma power dissipation p d 9 w operating ambient temperature t a 0 to 70 c storage temperature t stg C55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter s y mbol condition min. typ. max. unit su pp l y volta g e v cc 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc + 0.3 v low level input voltage v il ? 0.3 +0.8 v operating ambient temperature t a 0 70 c capacitance (t a = 25 c, f = 1 mhz) parameter s y mbol test condition min. typ. max. unit in p ut ca p acitance c i1 a0 - a11, ba0 ( a13 ) , ba1 ( a12 ) , /ras, 26 66 p f /cas, /we c i2 clk0, clk2 20 40 c i3 cke0 30 56 c i4 /cs0, /cs2 15 33 c i5 dqmb0 - dqmb7 3 17 data input/output capacitance c i/o dq0 - dq63, cb0 - cb7 4 13 pf
data sheet e0231n10 6 mc-4516ca727xfa dc characteristics (recommended operating conditions unless otherwise noted) -a75a -a75 parameter symbol test condition min. max. min. max. unit notes operating current i cc1 burst length = 1 /cas latency = 2 990 900 ma 1 t rc t rc(min.) , i o = 0 ma /cas latency = 3 990 945 precharge standby current in i cc2 p cke v il(max.) , t ck = 15 ns 9 9 ma power down mode i cc2 ps cke v il(max.) , t ck = 9 9 precharge standby current in non power down mode i cc2 n cke v ih(min.) , t ck = 15 ns, /cs v ih(min.) , input signals are changed one time during 30 ns. 180 180 ma i cc2 ns cke v ih(min.) , t ck = input signals are stable. 72 72 active standby current in i cc3 p cke v il(max.) , t ck = 15 ns 45 45 ma power down mode i cc3 ps cke v il(max.) , t ck = 36 36 active standby current in i cc3 n cke v ih(min.) , t ck = 15 ns, /cs v ih(min.) , 270 270 ma non power down mode input signals are changed one time during 30 ns. i cc3 ns cke v ih(min.) , t ck = , input signals are stable. 180 180 operating current (burst mode) i cc4 t ck t ck(min.) , i o = 0 ma /cas latency = 2 1,395 1,080 ma 2 /cas latency = 3 1,395 1,395 cbr (auto) refresh current i cc5 t rc t rc(min.) /cas latency = 2 2,430 2,070 ma 3 /cas latency = 3 2,430 2,160 self refresh current i cc6 cke 0.2 v 18 18 ma input leakage current i i(l) v i = 0 to 3.6 v, all other pins not under test = 0 v C 9 + 9 C 9 + 9 a output leakage current i o(l) d out is disabled, v o = 0 to 3.6 v C 1.5 + 1.5 C 1.5 + 1.5 a high level output voltage v oh i o = C 4 ma 2.4 2.4 v low level output voltage v ol i o = + 4 ma 0.4 0.4 v notes 1. i cc1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc1 is measured on condition that addresses are changed only one time during t ck (min.) . 2 . i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc4 is measured on condition that addresses are changed only one time during t ck (min.) . 3 . i cc5 is measured on condition that addresses are changed only one time during t ck (min.) .
data sheet e0231n10 7 mc-4516ca727xfa ac characteristics (recommended operating conditions unless otherwise noted) test conditions parameter value unit ac hi g h level in p ut volta g e / low level in p ut volta g e 2.4 / 0.4 v input timing measurement reference level 1.4 v transition time (input rise and fall time) 1 ns output timing measurement reference level 1.4 v t ck t ch t cl 2.4 v 1.4 v 0.4 v clk 2.4 v 1.4 v 0.4 v input t setup t hold output t ac t oh
data sheet e0231n10 8 mc-4516ca727xfa synchronous characteristics parameter symbol -a75a -a75 unit note min. max. min. max. clock cycle time /cas latency = 3 t ck3 7.5 (133 mhz) 7.5 (133 mhz) ns /cas latency = 2 t ck2 7.5 (133 mhz) 10 (100 mhz) ns access time from clk /cas latency = 3 t ac3 5.4 5.4 ns 1 /cas latency = 2 t ac2 5.4 6.0 ns 1 clk high level width t ch 2.5 2.5 ns clk low level width t cl 2.5 2.5 ns data-out hold time t oh 3.0 3.0 ns 1 data-out low-impedance time t lz 0 0 ns data-out high-impedance time /cas latency = 3 t hz3 3.0 5.4 3.0 5.4 ns /cas latency = 2 t hz2 3.0 5.4 3.0 6.0 ns data-in setup time t ds 1.5 1.5 ns data-in hold time t dh 0.8 0.8 ns address setup time t as 1.5 1.5 ns address hold time t ah 0.8 0.8 ns cke setup time t cks 1.5 1.5 ns cke hold time t ckh 0.8 0.8 ns cke setup time (power down exit) t cksp 1.5 1.5 ns command (/cs0, /cs2, /ras, /cas, /we, t cms 1.5 1.5 ns dqmb0 - dqmb7) setup time command (/cs0, /cs2, /ras, /cas, /we, t cmh 0.8 0.8 ns dqmb0 - dqmb7) hold time note 1. output load output z = 50 ? 50 pf remark these specifications are applied to the monolithic device.
data sheet e0231n10 9 mc-4516ca727xfa asynchronous characteristics parameter symbol -a75a -a75 unit note min. max. min. max. act to ref/act command period (operation) t rc 60 67.5 ns ref to ref/act command period (refresh) t rc1 60 67.5 ns act to pre command period t ras 45 120,000 45 120,000 ns pre to act command period t rp 15 20 ns delay time act to read/write command t rcd 15 20 ns act(one) to act(another) command period t rrd 15 15 ns data-in to pre command period t dpl 8 8 ns data-in to act(ref) command /cas latency = 3 t dal3 1clk+22.5 1clk+22.5 ns 1 period (auto precharge) /cas latency = 2 t dal2 1clk+20 1clk+20 ns 1 mode register set cycle time t rsc 2 2 clk transition time t t 0.5 30 0.5 30 ns refresh time (4,096 refresh cycles) t ref 64 64 ms note this device can satisfy the t dal3 spec of 1clk+20 ns for up to and including 125 mhz operation.
data sheet e0231n10 10 mc-4516ca727xfa serial pd (1/2) byte no. function described hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes 0 defines the number of bytes written into serial pd memory 80h 1 0 0 0 0 0 0 0 128 bytes 1 total number of bytes of serial pd memory 08h 0 0 0 0 1 0 0 0 256 bytes 2 fundamental memory type 04h 0 0 0 0 0 1 0 0 sdram 3 number of rows 0ch 0 0 0 0 1 1 0 0 12 rows 4 number of columns 0ah 0 0 0 0 1 0 1 0 10 columns 5 number of banks 01h 0 0 0 0 0 0 0 1 1 bank 6 data width 48h 0 1 0 0 1 0 0 0 72 bits 7 data width (continued) 00h 0 0 0 0 0 0 0 0 0 8 voltage interface 01h 0 0 0 0 0 0 0 1 lvttl 9 cl = 3 cycle time 75h 0 1 1 1 0 1 0 1 7.5 ns 10 cl = 3 access time 54h 0 1 0 1 0 1 0 0 5.4 ns 11 dimm configuration type 02h 0 0 0 0 0 0 1 0 ecc 12 refresh rate/type 80h 1 0 0 0 0 0 0 0 normal 13 sdram width 08h 0 0 0 0 1 0 0 0 8 14 error checking sdram width 08h 0 0 0 0 1 0 0 0 8 15 minimum clock delay 01h 0 0 0 0 0 0 0 1 1 clock 16 burst length supported 8fh 1 0 0 0 1 1 1 1 1, 2, 4, 8, f 17 number of banks on each sdram 04h 0 0 0 0 0 1 0 0 4 banks 18 /cas latency supported 06h 0 0 0 0 0 1 1 0 2, 3 19 /cs latency supported 01h 0 0 0 0 0 0 0 1 0 20 /we latency supported 01h 0 0 0 0 0 0 0 1 0 21 sdram module attributes 00h 0 0 0 0 0 0 0 0 22 sdram device attributes : general 0eh 0 0 0 0 1 1 1 0 23 cl = 2 cycle time -a75a 75h 0 1 1 1 0 1 0 1 7.5 ns -a75 a0h 1 0 1 0 0 0 0 0 10 ns 24 cl = 2 access time -a75a 54h 0 1 0 1 0 1 0 0 5.4 ns -a75 60h 0 1 1 0 0 0 0 0 6 ns 25-26 00h 0 0 0 0 0 0 0 0 27 t rp(min.) -a75a 0fh 0 0 0 0 1 1 1 1 15 ns -a75 14h 0 0 0 1 0 1 0 0 20 ns 28 t rrd(min.) -a75a 0fh 0 0 0 0 1 1 1 1 15 ns -a75 0fh 0 0 0 0 1 1 1 1 15 ns 29 t rcd(min.) -a75a 0fh 0 0 0 0 1 1 1 1 15 ns -a75 14h 0 0 0 1 0 1 0 0 20 ns 30 t ras(min.) 2dh 0 0 1 0 1 1 0 1 45 ns 31 module bank density 20h 0 0 1 0 0 0 0 0 128m bytes
data sheet e0231n10 11 mc-4516ca727xfa (2/2) byte no. function described hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes 32 command and address signal input setup time 15h 0 0 0 1 0 1 0 1 1.5 ns 33 command and address signal input hold time 08h 0 0 0 0 1 0 0 0 0.8 ns 34 data signal input setup time 15h 0 0 0 1 0 1 0 1 1.5 ns 35 data signal input hold time 08h 0 0 0 0 1 0 0 0 0.8 ns 36-61 00h 0 0 0 0 0 0 0 0 62 spd revision 12h 0 0 0 1 0 0 1 0 1.2 63 checksum for bytes 0 - 62 -a75a 80h 1 0 0 0 0 0 0 0 -a75 c1h 1 1 0 0 0 0 0 1 64 manufactures jedec id code 10h 0 0 0 1 0 0 0 0 nec 65-71 manufactures jedec id code 72 manufacturing location 73-90 manufactures p/n 91-92 revision code 93-94 manufacturing date 95-98 assembly serial number 99-125 mfg specific 126 intel specification frequency 64h 0 1 1 0 0 1 0 0 100mhz 127 intel specification /cas latency support ffh 1 1 1 1 1 1 1 1 timing chart refer to the pd45128441, 45128841, 45128163 data sheet (e0031n) .
data sheet e0231n10 12 mc-4516ca727xfa package drawing
data sheet e0231n10 13 mc-4516ca727xfa caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ic, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stress on these components to prevent damaging them. when re-packing memory modules, be sure the modules are not touching each other. modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. mde0107 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
mc-4516ca727xfa m01e0107 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] this product is not designed to be resistant to electromagnetic waves or radiation. this product must be used in a non-condensing environment. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

▲Up To Search▲

Price & Availability of MC-4516CA727XFA-A75A

	To Download MC-4516CA727XFA-A75A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .